The present invention relates to a memory testing device for large-capacity semiconductor memories such as those called flash memories.
As one possible solution to the problem of increased number of pins with the growth in memory capacity, there is now proposed a memory that uses I/O pins both as primarily intended data input/output pins and as command input pins, address input pins and so forth. As shown in FIG. 1, such a memory has, in addition to, for example, eight input/output pins I/O-1 to I/O-8, a command input control pin P.sub.CLE, an address input control pin P.sub.ALE, a write control pin P.sub.WE, a write inhibit control pin P.sub.WP, a chip selection control pin P.sub.CE and a read control pin P.sub.RE.
An address signal of a total of 8.times.3=24 bits can be input into the memory by applying it to the eight input/output pins I/O-1 to I/O-8 over three cycle periods, for instance. With the 24-bit address signal, it is possible to access a memory area having a storage capacity of 16 Mbits or so. Furthermore, an address signal of 8.times.4=32 bits can be input by applying it to the input/output pins over four cycle periods--this means that a memory area of an about 4-Gbit storage capacity can be accessed.
By time sharing the same pins and inputting thereinto an address signal over plural cycle periods as mentioned above, the memory capacity can be enlarged without increasing the number of pins. Hence, it is possible to construct memories of the same package structure but having different storage capacities.
FIG. 2 shows an example of operation timing of this kind of memory. Row D shows a sequence of signals that are applied to the input/output pins I/O-1 to I/O-8. This signal sequence is headed by a command signal C0 to C7, which is followed by an address signal A0 to A21 and by data DAT.
To input the command signal C0 to C7, the address signal A0 to A21 and the data DAT into the memory in distinction from one another, the command input control pin P.sub.CLE and the address input control pin P.sub.ALE are provided. By making H-logic a command input control signal CLE for input to the command input control pin P.sub.CLE as shown in Row D, the command signal C0 to C7 is read into the memory. When an address input control signal ALE for input to the address input control pin P.sub.ALE is held H-logic as shown in Row B, signals applied to the input/output pins I/O-1 to I/O-7 are read as the address signal A0 to A21 into the memory, by which an access is made to an address desired to write data or address to read out data. FIG. 2 shows the cases where the 22-bit address signal A0 to A21 is supplied for three cycle periods to access a memory of a 4-Mbyte storage capacity and where the data DAT.sub.1 to DAT.sub.n is applied to the input/output pins I/O-1 to I/O-8 on a time sharing basis to write the data into the memory.
FIG. 3 shows in detail examples of signals that are applied to the input/output terminals I/O-1 to I/O-8. In cycle 1 eight bits of the command signal C0 to C7 is applied to the input/output pins I/O-1 to I/O-7. In cycle 2 the first eight bits A0 to A7 of the address signal are provided. This address signal will hereinafter be referred to as a column address signal (or X address). In cycle 3 eight bits A8 to A15 of the address signal are provided. The address signal will hereinafter be referred to as a NAND address signal (or Y address). In cycle 4 six bits A16 to A21 of the address signal are provided. This address signal will hereinafter be referred to as a block address (or Z address). The address signal A0 to A21 is followed by respective bits D0 to D7 forming the data DAT.sub.1.
As described above, in the case of a memory of the type using the input/output pins both as data input/output pins and as input pins such as address input pins and command input pins, it is necessary to supply different kinds of signals to each of the input/output pins I/O-1 to I/O-8 as shown in FIG. 3. This is a requirement that a memory testing device for this kind of memories is also required to meet; namely, to test this kind of memories, a command signal, an address signal and data need to be input to input/output pins I/O-1 to I/O-8.
As depicted in FIG. 4, the memory testing device is basically made up of: a pattern generator 11; pattern select means 12 that selects various kinds of pattern signals output from the pattern generator 11 to take out pattern data to be provided to each pin;a formatter 13 for converting the pattern data, taken out by the pattern select means 12, to a pattern signal having a real waveform; a driver 14 for applying the pattern signal, generated by the formatter 13, to a memory under test MUT; a level comparator 15 that decides and takes in the logical level of a signal read out of the memory MUT; a logical comparator 16 for comparing the logical level, decided by the level comparator 15, with expectation data; a failure analysis memory 17 which, when a mismatch is detected by the logical comparator 16, that is, when a defective cell is detected in the memory MUT, stores at the address of the defective cell a logical value indicating its defectiveness and reads out and uses the stored value for a failure analysis; a timing signal generator 18 for applying timing signals to the pattern generator 11, the pattern select means 12, the formatter 13, the driver 14, the level comparator 15 and the logical comparator 16; and a tester processor 10 that governs the whole memory testing device.
In FIG. 3, the pattern selector 12, the formatter 13, the driver 14 and the level comparator 15 are each represented by one block, but in practice, each block has channels of the same number as that of pins of the memory MUT so that the pattern signal is fed to each pin.
Conventionally, a control signal that is provided under the control of a program in the tester processor 10 is applied via a data bus DBUS and a control bus CBUS to the pattern selector 12, which selects the pattern signal to be applied to each pin of the memory MUT. Hence, in the case of selecting different kinds of signals such as the command signal, the address signal and the data for each of the input/output pins I/O-1 to I/O-8 as described above, the contents of the program in the tester processor 10 is complex and the preparation of such a program requires much labor and complicated work, and hence it is highly expensive. This will be described below.
In the tester processor 10 there is provided a bus register 10R, in which a pin condition PD of the memory under test is set. The pin condition for the pins I/O-1 to I/O-8 is described, for example, as follows: EQU PD1-8=IN1,XOR,ACLK1,BCLK1,CCLK1,SDM,RDSM&lt;X0-7,Y0-7,D0-7&gt;
IN1 sets the pins I/O-1 to 1/O-8 in an input mode, XOR, ACLK1, BCLK1 and CCLK1 designate waveform combining logic and the kind of clock for use in the formatter 13, SDM designates the generation of the Y address for two successive cycles and RDSM designates the kind of data. &lt;X0-7,YO-7,DO-7&gt; designates the kind of pattern (X address, Y address, data) that is applied to the pins I/O-1 to I/O-8. Since the present invention is related particularly to the kind of pattern mentioned last, the pin condition will hereinafter be expressed merely as PD=&lt;A,B,C,D&gt; That is, in the case of the memory MUT in the example of FIG. 1, a description of a pin condition PD1-8 on the pins I/O-1 . . . , I/O-8 as PD1-8=&lt;X0-7,Y0-7,C0-7,D0-7&gt;, for example, indicates that when the X address is provided to the memory MUT, addresses XO, . . . , X7 are fed to the pins I/O-1, . . . , I/O-8, respectively, and that when the Y address is provided to the memory MUT, addresses Y0, . . . , Y7 are fed to the pins I/O-1, . . . , I/O-8, respectively. The same goes for the cases of commands C0, . . . , C7 and data D0, . . . , D7 are provided to the memory MUT.
In the conventional memory testing device, the description of the pin condition is limited to only three kinds of information because of restrictions on the hardware structure of the device. However, to test recent flash memories of large address sizes, it is necessary to apply the command c, the X address, the Y address, the Z address and the data D to the I/O pins I/O-1 to I/O-8 in a desired sequence as referred to previously with reference to FIG. 2. To meet this requirement, in the prior art, PD1-8=&lt;T0-7,Z0-7,C0-7,D0-7&gt;, for instance, is set as the pin condition in the bus register and prior to the generation of the Y address, for example, in a program for the pattern generation by the pattern generator (an instruction sequence), a multiplexer is controlled to generate the X address X0-7 of one cycle by interruption as described later on. This will be described below with reference to FIG. 5.
FIG. 5 shows, in simplified form, the pattern generator 11 in the conventional memory testing device of FIG. 4 and the formatter 13 provided corresponding to one I/O pin of the MUT. A sequence controller 11A of the pattern generator 11 provides an address of an instruction memory 11B, where an instruction to be executed is described, to an instruction address field 11B1 and generates the next address, following a sequence instruction described at that address. When the address is provided to the instruction address field 11B1 of the instruction memory 11B, instructions/data described in a sequence instruction field 11B2, a test address field 11B3, a test data field 11B4, an MUT field 11B5 and a control field 11B6 corresponding to that address are read out and the instructions are executed, by which data is set. As the result of this, sequence control instructions (INC, NOP, JUMP, etc.) for proceeding to an instruction address to be executed next, described in the sequence instruction field 11B2, are provided to the sequence controller 11A, then addresses in X-, Y- and Z-address calculators 11CX, 11CY and 11CZ of an calculation part 11C are calculated following a calculation instruction in the test address field 11B3, then data in the test data field 11B4 are output to data registers 11D1 and 11D2, then a MUT control signal C in the MUT field 11B5 is output, and selection control signals for a multiplexer 11E and the pattern selector 12 in the control field 11B6 are output. In this way, the pattern generator 11 generates, more than 100 kinds of patterns that are bit sequences of respective pattern data of an address pattern (22 bits, for example,) a data pattern (32 bits, for instance), a command pattern (8 bits, for instance) and so forth, and all the patterns are provided to the pattern selector 12 corresponding to each pin of the MUT.
In FIG. 5 there is shown only one pattern selector 12, but it is provided corresponding to each pin of the MUT. Each pattern selector 12 selects and outputs test patterns of address, data and command that are provided to the corresponding pin of the MUT via the formatter 13 and the driver 14. As indicated by the broken line, the pattern selector 12 also selects and outputs respective bits of expectation data set in the data register 11D2 for logical comparison with data read out of the MUT, but since this is not directly related to the present invention, no description will be given.
A multiplexer 12G of each pattern selector 12 determines which pattern is to be currently applied to the corresponding I/O pin, the X address, Y address, Z address, command C or data D, and which one of the eight I/O pins the pattern selector 12 corresponds to, based on a select signal (X, Y, Z, C, or D) from the control field 11B6 written in a register 12R and the pin condition PD provided from a path register 10R.
Conventionally, the address size of the memory under test is small, for example, 16-bit or less, so that in the case of inputting the address via the pin I/O-1 to I/O-8, for instance, a two-cycle address write (i.e. a write of the X address X0, . . . ,X7 and a write of the Y address Y0, . . . ,Y7) is enough; hence, the pin condition that is preset in the path register 10R needs only to be four kinds of data such as PD=&lt;X0-7,Y0-7,C0-7,D0-7&gt;. However, some of recent flash memories have address sizes larger than 16 bits, in which case the two-cycle address write is not enough to store all address bits. Therefore, the conventional testing device cannot be used to test such large-capacity memories. To settle this problem, it is necessary in the prior art that the description of the pin condition in the bus register set, for example, PD=&lt;Y0-7,Z0-7,C0-7,D0-7&gt;, about four kinds of data as mentioned above and that an instruction step to be stored in the instruction memory 11B be described so that the pattern generator 11 causes an interruption of one cycle for each Y address generating step and controls its multiplexer 11E (see FIG. 5) with the interruption cycle to select and output the X address. Hence, the preparation of the instruction program for the pattern generation is time-consuming accordingly.